On 06/25/2013 01:06 AM, tiansworld wrote:
Hi Pete,
Seems there is problem on Circuit Design section.
The Circuit Design in each of the test builds(French, Japanese, Ukrainian and Chinese) are untranslated. But they it's translated in transifex.

The PO file in transifex contains more strings than the published one. I guess there are strings from Fedora 18 which prevents the Fedora 19 new strings been published.




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Okay, I purged POTs and am refreshing transifex now, check in a few minutes.
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