commit a27a36d27719f78bccdf831798941c666860f87a
Author: Dave Airlie <airlied(a)redhat.com>
Date: Fri Apr 1 14:27:54 2011 +1000
Revert upstream patches causing SNB regression.
mesa-intel-snb-regression-reverts.patch | 125 +++++++++++++++++++++++++++++++
mesa.spec | 7 ++-
2 files changed, 131 insertions(+), 1 deletions(-)
---
diff --git a/mesa-intel-snb-regression-reverts.patch
b/mesa-intel-snb-regression-reverts.patch
new file mode 100644
index 0000000..9b33f62
--- /dev/null
+++ b/mesa-intel-snb-regression-reverts.patch
@@ -0,0 +1,125 @@
+diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
+index 32ee37f..21ce92c 100644
+--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
++++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
+@@ -52,35 +52,6 @@ static void guess_execution_size(struct brw_compile *p,
+ }
+
+
+-/**
+- * Prior to Sandybridge, the SEND instruction accepted non-MRF source
+- * registers, implicitly moving the operand to a message register.
+- *
+- * On Sandybridge, this is no longer the case. This function performs the
+- * explicit move; it should be called before emitting a SEND instruction.
+- */
+-static void
+-gen6_resolve_implied_move(struct brw_compile *p,
+- struct brw_reg *src,
+- GLuint msg_reg_nr)
+-{
+- struct intel_context *intel = &p->brw->intel;
+- if (intel->gen != 6)
+- return;
+-
+- if (src->file == BRW_ARCHITECTURE_REGISTER_FILE && src->nr ==
BRW_ARF_NULL)
+- return;
+-
+- brw_push_insn_state(p);
+- brw_set_mask_control(p, BRW_MASK_DISABLE);
+- brw_set_compression_control(p, BRW_COMPRESSION_NONE);
+- brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD),
+- retype(*src, BRW_REGISTER_TYPE_UD));
+- brw_pop_insn_state(p);
+- *src = brw_message_reg(msg_reg_nr);
+-}
+-
+-
+ static void brw_set_dest(struct brw_compile *p,
+ struct brw_instruction *insn,
+ struct brw_reg dest)
+@@ -1800,7 +1771,6 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
+ GLuint bind_table_index)
+ {
+ struct intel_context *intel = &p->brw->intel;
+- struct brw_reg src = brw_vec8_grf(0, 0);
+ int msg_type;
+
+ /* Setup MRF[1] with offset into const buffer */
+@@ -1817,7 +1787,6 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
+ addr_reg, brw_imm_d(offset));
+ brw_pop_insn_state(p);
+
+- gen6_resolve_implied_move(p, &src, 0);
+ struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+
+ insn->header.predicate_control = BRW_PREDICATE_NONE;
+@@ -1826,7 +1795,7 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
+ insn->header.mask_control = BRW_MASK_DISABLE;
+
+ brw_set_dest(p, insn, dest);
+- brw_set_src0(insn, src);
++ brw_set_src0(insn, brw_vec8_grf(0, 0));
+
+ if (intel->gen == 6)
+ msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
+@@ -1997,7 +1966,20 @@ void brw_SAMPLE(struct brw_compile *p,
+ {
+ struct brw_instruction *insn;
+
+- gen6_resolve_implied_move(p, &src0, msg_reg_nr);
++ /* Sandybridge doesn't have the implied move for SENDs,
++ * and the first message register index comes from src0.
++ */
++ if (intel->gen >= 6) {
++ if (src0.file != BRW_ARCHITECTURE_REGISTER_FILE ||
++ src0.nr != BRW_ARF_NULL) {
++ brw_push_insn_state(p);
++ brw_set_mask_control( p, BRW_MASK_DISABLE );
++ brw_set_compression_control(p, BRW_COMPRESSION_NONE);
++ brw_MOV(p, retype(brw_message_reg(msg_reg_nr), src0.type), src0);
++ brw_pop_insn_state(p);
++ }
++ src0 = brw_message_reg(msg_reg_nr);
++ }
+
+ insn = next_insn(p, BRW_OPCODE_SEND);
+ insn->header.predicate_control = 0; /* XXX */
+@@ -2052,7 +2034,17 @@ void brw_urb_WRITE(struct brw_compile *p,
+ struct intel_context *intel = &p->brw->intel;
+ struct brw_instruction *insn;
+
+- gen6_resolve_implied_move(p, &src0, msg_reg_nr);
++ /* Sandybridge doesn't have the implied move for SENDs,
++ * and the first message register index comes from src0.
++ */
++ if (intel->gen >= 6) {
++ brw_push_insn_state(p);
++ brw_set_mask_control( p, BRW_MASK_DISABLE );
++ brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD),
++ retype(src0, BRW_REGISTER_TYPE_UD));
++ brw_pop_insn_state(p);
++ src0 = brw_message_reg(msg_reg_nr);
++ }
+
+ insn = next_insn(p, BRW_OPCODE_SEND);
+
+@@ -2162,7 +2154,17 @@ void brw_ff_sync(struct brw_compile *p,
+ struct intel_context *intel = &p->brw->intel;
+ struct brw_instruction *insn;
+
+- gen6_resolve_implied_move(p, &src0, msg_reg_nr);
++ /* Sandybridge doesn't have the implied move for SENDs,
++ * and the first message register index comes from src0.
++ */
++ if (intel->gen >= 6) {
++ brw_push_insn_state(p);
++ brw_set_mask_control( p, BRW_MASK_DISABLE );
++ brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD),
++ retype(src0, BRW_REGISTER_TYPE_UD));
++ brw_pop_insn_state(p);
++ src0 = brw_message_reg(msg_reg_nr);
++ }
+
+ insn = next_insn(p, BRW_OPCODE_SEND);
+ brw_set_dest(p, insn, dest);
diff --git a/mesa.spec b/mesa.spec
index d08c55a..9dcab1b 100644
--- a/mesa.spec
+++ b/mesa.spec
@@ -18,7 +18,7 @@
Summary: Mesa graphics libraries
Name: mesa
Version: 7.11
-Release: 0.4.%{gitdate}.0%{?dist}
+Release: 0.5.%{gitdate}.0%{?dist}
License: MIT
Group: System Environment/Libraries
URL:
http://www.mesa3d.org
@@ -31,6 +31,7 @@ Source2: %{manpages}.tar.bz2
Source3: make-git-snapshot.sh
Source4: llvmcore.mk
+Patch1: mesa-intel-snb-regression-reverts.patch
Patch2: mesa-7.1-nukeglthread-debug.patch
Patch3: mesa-no-mach64.patch
Patch4: legacy-drivers.patch
@@ -214,6 +215,7 @@ Requires: Xorg %(xserver-sdk-abi-requires ansic)
%(xserver-sdk-abi-requires vide
%prep
#setup -q -n Mesa-%{version}%{?snapshot} -b0 -b2
%setup -q -n mesa-%{gitdate} -b2
+%patch1 -p1 -b .intel-fix
%patch2 -p1 -b .intel-glthread
%patch3 -p1 -b .no-mach64
%patch4 -p1 -b .classic
@@ -485,6 +487,9 @@ rm -rf $RPM_BUILD_ROOT
%{_libdir}/libOSMesa.so
%changelog
+* Fri Apr 01 2011 Dave Airlie <airlied(a)redhat.com> 7.11-0.5.20110401.0
+- Revert upstream patches causing SNB regression.
+
* Fri Apr 01 2011 Dave Airlie <airlied(a)redhat.com> 7.11-0.4.20110401.0
- upstream snapshot again - proper fix for ILK + nv50 gnome-shell issue